Wafer

Demanding Korean suppliers beat Chinese pricing while building 100,000 wafers per month misunderstands semiconductor supply economics. Wafer fab tools and pure chemical consumables are priced by yield and purity, not procurement leverage.…

Expert call covering InP substrates – CPO & high-power CW laser demand drivers, 3" to 4"/6" wafer size transition, yield bottlenecks, raw phosphorus constraints, and 2H27/2028 market balance outlook. $AXTI https://t.co/hZfgeYxImE

CHINA'S CXMT DRAM CAPACITY SEEN JUMPING 31% IN 2027, COULD NEARLY DOUBLE BY 2028 According to market research firms Counterpoint Research and TrendForce on the 18th, CXMT's monthly DRAM wafer production capacity is expected to expand from…

J.P. Morgan: We expect A14 to go into mass production in 1H28, which could generate some revenue in 2H28. We believe the tight leading edge wafer supply will extend into 2027-208 and expect TSMC to continue its accelerated capacity build…

A US class action alleges Samsung, SK hynix and Micron coordinated DRAM pricing, and that each AI HBM bit cost about three bits of regular DRAM. These are unproven allegations: no certified class, no liability found. Wafer conversion math…

TSMC’s wafer ASP gap with UMC, GlobalFoundries and Samsung keeps widening. TSMC is setting new blended ASP highs while most peers remain below their previous peaks. Per our Foundry Model, from 2Q22 to 2Q26, TSMC’s wafer revenue share…

$MU went from 16 to 26 strategic customer agreements in a single quarter, and now @elonmusk is calling Micron the reasonable one on future memory prices while its peers have been “extortionate.” Those contracts now cover more than 35% of…

SEMI: silicon interposers break down at scale. Intel CPU packages went from about 45x45mm to over 100x100mm, now 120x120mm. At 100x100mm a 300mm wafer yields four interposers or fewer. Bridges lead the next generation; glass substrates…

Empyrean reports that China's domestic EDA tools now cover up to 85% of all the processes. In FPD, memory & wafer production, domestic EDA tool already have > 50% mkt share. It's been a while since Empyrean said it reached 7nm logic…

$VICR is up nearly 50% since I posted my deep dive last month, and I think this run is still early. Exactly four analysts cover this company. Four, for a $12 billion name sitting on the nastiest problem in AI hardware. A wafer-scale AI…

Goldman Sachs is now forecasting a 4.9 percent DRAM undersupply for 2026, and the mechanism behind that number matters more than the headline. Samsung, SK Hynix, and Micron aren't short on fab capacity. They're reallocating it. HBM for AI…

Memory market spot prices: DRAM: > 4Gb DDR4: +274% > 4Gb DDR3: +243% > 16Gb DDR5: +100% > 8Gb DDR4: +92% > 16Gb DDR4: +30% NAND / Storage: > 256Gb Wafer: +167% > 512GB SSD: +144% > 512Gb Wafer: +44% $SNDK $MU $DRAM $EWY $SKHY

How is a lightning-fast pace of 10 chip designs a year even possible? 🤯 💡 Here’s my take: Terafab’s path to faster chip development starts with the research fab at Giga Texas. By bringing mask-making, fabrication, packaging, and testing…

Every Robotaxi and Optimus bot needs memory to turn AI models into real-world action. As Tesla scales production, locking down that memory supply is becoming a critical pillar of its manufacturing strategy—and that’s precisely why Terafab…

HBM needs ~3x the wafer area of DDR5 for equal capacity and sells at ~5x the per-bit price (Micron, Hot Chips 2026). The diversion shows up in commodity DRAM: contract prices reportedly rose 90-95% QoQ in Q1 2026 and another 58-63% in Q2.…

Terafab could bring Tesla’s experience building custom factory equipment into one of the world’s most demanding industries 🔥 During the X Takeover talk, @elonmusk described how he wants to get there: start with conventional equipment,…

Wafer shipping boxes are a bottleneck too. 3S Korea is doubling FOSB capacity at Anseong to 30,000 units a month from 15,000, and has taken control of a Suzhou unit whose Zhangjiagang plant can build 100,000. Wafer carrier revenue rose…

Expert Call: Memory - Key Takeaways > Contracts are moving from flexible 2–3 year terms to 5yr+ take-or-pay structures with upfront deposits and price floors/ceilings, prioritizing downside protection for suppliers. > Tight conventional…

AI & TECH STOCK MARKET REVIEW The 10 biggest stories from today: 1. $NVDA hit another ATH and is close to becoming the first company ever worth $6 trillion. The stock is up ~28% this year, adding ~$1.2 trillion in market cap, making Nvidia…

Samsung reportedly lifts HBM wafer starts from ~180,000/month to 250,000 in 2027, HBM4/HBM4E share from 40% to 80% of shipments. Glass carrier buys go 20,000 to 50,000 sheets a month. Consumables, not slides, mark a real ramp.…

Capital only buys the cleanroom. Advanced lithography and deposition tools get a fab to the starting line. Sustained wafer yield comes down to the process engineers on the floor managing drift. https://t.co/PZIPnPS6Yw

Samsung: HBM could take nearly 30% of industry DRAM wafer capacity in 2027, up from ~20% today. TrendForce sees blended HBM ASPs +121% y/y in 2027; some GPU/ASIC designs weigh 8-high stacks to stretch bit supply. Conventional DRAM is the…

No arms. No rails. No contact. For decades, moving a wafer meant a robot arm: joints, belts, bearings. Every arm is a particle source, a maintenance item, and a constraint on tool placement. Magnetically levitated XBots: six degrees of…

The pattern I keep seeing this month: once a model layer commoditizes, the fight moves one layer down to whoever serves it fastest. RunAnywhere, a YC W26 company, launched Wally this week, an inference stack for open frontier models that…

Bernstein: We project CXMT's wafer capacity share may surpass Micron in 2028, reaching nearly 20% globally. $MU $DRAM $DISK $EWY

Importance of CXMT in China's AI buildout can be seen in these Atlas SuperNode comparison. Despite going from 384 to 1024 chips, HBM size only doubled & overall DRAM only increased by 1/3. Atlas-960 w/ 4096 cards expect to have 1 PB HBM,…

CXMT G5 platform is a huge deal. It results in competitive LPDDR5X/6 product (of 24Gb die) to be used in producing 24 GB DRAM. Allows CXMT catch up to Big 3 in bits per wafer & various power consumption properties. G5 platform can be used…

🇨🇳 China’s leading memory-chip maker, CXMT, says its fifth-generation chip platform has entered mass production, marking a new step in the country’s push to expand domestic semiconductor manufacturing. The company also unveiled two…

Semiconductor Value Chain: Chemicals & Materials Every semiconductor starts with a reliable supply of critical materials. Specialty chemicals, ultra-high-purity chemicals, fluorochemicals and advanced materials form an essential part of…

🇨🇳 Chinese chipmaker CXMT announced that its fifth-generation DRAM memory chip platform has entered mass production. This milestone could position it as a stronger rival to Samsung, SK Hynix, and Micron globally. The new platform packs…

This is one of the important chart in the entire memory market (Save this). For two decades, DRAM prices followed the red dotted line, a steady, relentless decline driven by Moore's Law and more efficient manufacturing. That red dotted…

https://t.co/akpmxgXjk4 Where Can India Actually Be Strong in Semiconductor Industry ? This is probably the part I found most interesting while reading about the semiconductor ecosystem. India doesn’t necessarily need to become good at…

Tech roadmaps require deep operational alignment. Software algorithms advance quickly across borders. The lasting advantage belongs to nations that master physical wafer fabrication and power distribution. https://t.co/bUZXXt2Wal

Testing is the one part of the AI buildout that is not optional. A single bad die takes the whole package with it. So the more expensive the chips get, the more testing happens, not less. My two favorite plays are $AEHR and $FORM. $FORM…

$210 billion in wafer fab equipment spend projected for 2027 tracks the physical ceiling on hardware delivery. When DRAM tooling alone requires $85 billion in annual capital expenditure, lead times on lithography and deposition tools…

Samsung Foundry filling 2nm line capacity at the Taylor fab before initial runs begin shows where automotive and edge computing demand is landing. When vehicle architectures shift toward centralized domain compute, wafer allocation becomes…

Advanced packaging and wafer yield dictate autonomy timelines. Automotive compute stacks cannot scale when dependent on standard foundry allocation queues. OEMs treating silicon as strategic infrastructure will control their deployment…

Myron Xie joins @JordanNanos on why NVDA's Rubin Ultra preview had 1TB of HBM per package vs the 192GB that ships. It comes down to supply and not performance, why 4-HI more than doubles the cubes you can harvest per wafer, why the loudest…

Garen Semi became world's 1st company to grow 12-inch Gallium oxide single crystal wafer using its self developed SCIENCE series VB growth equipment. This happened after it was 1st globally to grow 8-inch Epitaxy back in March. Garen is…

Cleanroom capex creates the facility, but specialized gas purity, vacuum valves, and metrology tooling determine commercial output. Sub-tier equipment suppliers from Japan remain the load-bearing foundation that dictates operational wafer…

Advanced packaging substrates from Japanese suppliers like Ibiden and Shinko are the true physical bottleneck in accelerated compute. Front-end wafer capacity cannot clear customer delivery schedules without multi-layer ceramic and organic…

Two bets on HBM interconnect. TSMC, per ETNews, has asked suppliers for 5-micrometre-class microbump bonding and underfill — keep scaling bumps. Samsung is going the other way: bumpless hybrid copper bonding plus multi-wafer bonding for…

Memory just delivered $306 billion of pure price increase in seven months (Save this). Bernstein's decomposition is the cleanest sign yet that this cycle behaves differently from every prior memory upturn. Of the roughly $453 billion in…

Aluminum Oxide is emerging as a photonic integrated circuit (PIC) platform that addresses the limitations of silicon-based photonics. It offers a broad optical transparency range (UV to mid-infrared), ultra-low optical losses, high power…

$VICR held a world record in 2017 for the exact architecture the entire AI industry is racing toward now. Then the story disappeared. Here's the setup. Power loss scales with the square of current, not power. Double the current, you burn…

SemiAnalysis on memory for robots: "Although total DRAM wafer capacity continues to grow, most of the incremental capacity is being absorbed by HBM for AI accelerators. That leaves the commodity and LPDDR supply that robot brains depend on…

SK keyfoundry signed an 11-year deal to supply Elmos with 130nm capacity through 2037, after 18 years on 350nm; wafer prices can be adjusted under the agreement. 200mm supply is tightening as TSMC and Samsung shift to 300mm. Legacy nodes…

This is WILD! Nomura thinks memory becomes a $3.7 trillion market by 2030, bigger than the entire semiconductor industry is today. The chart shows that the global memory revenue goes from $185 billion in 2024 to $270 billion in 2025, then…

Advanced packaging and interposer capacity remain the structural pacing items for high-performance silicon. Front-end wafer starts mean little if back-end substrates and thermal packaging cannot clear testing queues. https://t.co/3tFYZ58Zx2

DRAM, HBM, and NAND supply to remain right in 2028. > The capacity squeeze effect of high bandwidth memory (HBM) may continue into 2028. Analysts point out that HBM's share of overall DRAM wafer starts will rise from 19% in 2026 to 28% in…

Advanced packaging and automotive silicon demand are absorbing foundry capacity years before volume rollouts. Dedicated in-vehicle compute architectures require guaranteed wafer allocations to survive automotive production cycles.…

Scaling photomask geometry to 12 inches addresses throughput limits in advanced lithography. Sub-2nm fabrication and multi-layer memory stacks require rewriting the entire toolchain, from mask inspection to wafer handling robotics.…

The biggest memory cycle in 45 years is only getting started (Save this). Every prior peak on this chart came from a demand event that ended, whether that was the Iraq war build, the cloud capex boom or COVID. Each one produced a sharp red…

IDM vs. Fabless vs. Foundry : Who Creates OSAT Demand? 1. IDM ( Integrated Device Manufacturer) IDMs such as Intel, Texas Instruments and STMicroelectronics design and manufacture their own chips. Historically, they have also handled much…

OSAT Back-End Process Flow : Legacy to Advanced Wafer In From Foundry (~300mm wafer) ↓ Wafer Test Probe & test individual dies ↓ Dicing / Singulation Separate wafer into individual dies ↓ Die Attach Mount die onto substrate / leadframe ↓…

https://t.co/ROO1TcKNl0 Think about a semiconductor as one small part of a much larger manufacturing chain. A simplified version looks something like: Design → Wafer Fabrication → OSAT → Electronics/PCB Assembly → Final Product A…

OSAT (Outsourced Semiconductor Assembly and Testing ) Think about a semiconductor as one small part of a much larger manufacturing chain. A simplified version looks something like: Design → Wafer Fabrication → OSAT → Electronics/PCB…

CPO is moving test upstream. Chroma says optical engines are now screened before final packaging: optical test is slow and downstream failure expensive. Suppliers are pushing detection to the wafer stage. Where the defect is caught becomes…

Deploying leading-edge wafer fabs overseas requires duplicating dense Tier 2 chemical refining corridors and precision sub-component suppliers. Without localized ecosystem depth, operational costs and tool maintenance lead times remain…

Building sovereign RISC-V compute accelerators solves design IP independence. The real operational moat remains securing leading-edge foundry wafer allocations and establishing a mature compiler stack to support low-latency inference…

Expanding dedicated advanced packaging hubs underscores that backend assembly and testing have become equal partners to wafer lithography in delivering next-generation AI compute clusters. https://t.co/l8xuymi71s

Post Log in Sign up Post wafer on X: "We’re excited to announce that we’ve raised a $40M Series A! co-led by @MarathonMP and @chemistry, with participation from @Wing\VC, @AMD Ventures, @outsetcap, @fiftyyears, and @ycombinator, and our…

SubscribeSign in Cerebras's Next Generation CS-4: Fast Just Got Faster Double the Performance, Double the Power, Double the Fun Myron Xie, Bryan Shan, Wega Chu, and 2 others Aug 18, 2026 ∙ Paid 136 6 Share Cerebras revealed CS-4 this week,…